Chinese tech giant Huawei has launched a new revolutionary semiconductor design framework to counter strict U.S. export controls. In a major tech forum, the company said it plans to achieve high-end computing performance comparable to a leading-edge 1.4-nanometer process by 2031, thus narrowing the gap with global leaders such as TSMC.
With Washington blocking China’s access to the advanced extreme ultraviolet (EUV) lithography machines needed for traditional manufacturing, Huawei is moving away from conventional methods. Rather than focusing only on shrinking transistor sizes—an industry trend known as Moore’s Law that is already approaching atomic-scale limits—Huawei introduced what it calls the “Tau Scaling Law.”
This new engineering principle focuses on system-level efficiency rather than physical miniaturization. Under this strategy, performance gains are achieved by drastically reducing internal signal delays, shortening internal wiring paths, and lowering latency. Huawei’s upcoming “LogicFolding” architecture will put this theory into practice. The company revealed that its next-generation Kirin smartphone chips, scheduled to debut in late 2026, will be the first to feature this architecture to boost processing speeds.
The breakthrough comes at a key moment for China’s domestic tech ecosystem. With the U.S. blocking the most advanced artificial intelligence processors from Nvidia from entering the Chinese market, demand for domestic alternatives has soared. Huawei’s Ascend AI series has already become crucial to powering prominent local AI models. Huawei is designing chips that optimize data movement instead of relying on restricted manufacturing equipment, in a bid to create a self-sufficient path forward for China’s smartphone and artificial intelligence industries.